Presentation

The memory subsystem in a microprocessor is crucial for scaling the performance/watt of future computing devices. To be efficient, every part of the memory subsystem must be highly optimized, most notably the multi-level cache hierarchy and networks-on-chip. A team of researchers from Chalmers University, noticed the existing interconnect and cache coherence solution does not scale well to meet the needs for upcoming products with a larger number of processor cores. The IPs designed by the Chalmers team solve this scalability issue. More specifically, in the context of various projects, including the European Processor Initiative, the research team has developed intellectual property (IP) blocks of crucial memory subsystem components. This includes a coherent home node, a system-level cache, and a network-on-chip, each IP meticulously optimized for high performance. The IP blocks already have a Technical Readiness Level (TRL) of up to 7 and Innovation Readiness Level (IRL) of up to 5.